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Ordering number : EN5931
CMOS IC
LC723732/40/48/56/64
ETR Microcontrollers
Overview
The LC723700 Series are large-capacity ETR microcontrollers that achieve an instruction execution time of 1.33 s and provide up to 64 KB of ROM and up to 2 KB of RAM. They include an on-chip high-performance PLL circuit that features an added high-speed lock circuit and can control the C/N characteristics of a local oscillator. They also provide a rich set of on-chip interface circuits, including a 3-channel serial I/O port, and an 8input 8-bit A/D converter.
* *
Functions
* ROM -- Up to 32K steps (32,767 x 16 bits) -- The subroutine area holds 4 K steps (4,096 x 16 bits) * RAM -- Up to 4 K x 4 bits (In banks 00 through 3F) LC723732 - ROM: 32 KB, RAM 1 KB LC723740 - ROM: 40 KB, RAM 2 KB LC723748 - ROM: 48 KB, RAM 2 KB LC723756 - ROM: 56 KB, RAM 2 KB LC723764 - ROM: 64 KB, RAM 2 KB * Stack -- 32 levels * Serial I/O -- Three channels. These circuits can support both 2wire and 3-wire 8-bit communication techniques, and can be switched between MSB first and LSB first operation. -- One of six internally generated serial transfer clock rates can be selected: 12.5, 37.5, 187.5, 281.25, 375, and 450 kHz. * External interrupts -- Seven interrupt inputs (pins INT0 through INT5, and the HOLD pin) These interrupts can be set to switch between rising and falling edges, although the HOLD pin only supports falling edge detection. * Internal interrupts -- Seven interrupts; four internal timer interrupts, and three serial I/O interrupts. * Interrupt nesting levels -- 16 levels -- Interrupt are prioritized in hardware as follows:
*
*
*
*
*
HOLD pin > INT0 pin > INT1 pin > INT2 pin > INT3 pin > INT4 pin > INT5 pin > S-I/O0 > S-I/O1 > S-I/O2 > internal TMR0 > internal TMR1 > internal TMR2 > internal TMR3 A/D converter -- 8-bit resolution and 8 inputs General-purpose ports -- Input ports: 12 -- Output ports : 4 -- I/O ports: 62 (These pins can be switched between input and output in 1-bit units.) PLL block -- Includes a sub-charge pump for high-speed locking. -- Supports dead zone control. -- Built-in unlock detection circuit. -- Twelve reference frequencies: 1, 3, 3.125, 5, 6.25, 9, 10, 12.5, 25, 30, 50, and 100 kHz. -- A second PLL circuit is also included for use in AM up conversion. Universal counter -- This 20-bit counter can be used for either frequency or period measurement and supports four measurement (calculation) periods: 1, 4, 8, and 32 ms. Timers -- Two fixed timers and two programmable timers (8bit counters) TMR0: Supports four periods: 10 s, 100 s, 1 ms, and 5 ms TMR1: Supports four periods: 10 s, 100 s, 1 ms, and 10 ms TMR2 and TMR3: Programmable 8-bit counters. Input clocks with 10 s, 100 s, and 1 ms periods are provided. -- One 125-ms timer flip-flop provided. Beep circuit -- Provides 12 fixed beep tones: 0.5, 1, 2, 2.08, 2.2, 2.5, 3.33, 3.75, 4.17, and 7.03 kHz. -- Programmable 8-bit beep tone generator. Reference clocks with frequencies of 5 kHz, 15 kHz, and 50 kHz are provided. Reset -- Built-in voltage detection reset circuit -- External reset pin
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51398RM (OT) No.5931-1/14
LC723732/40/48/56/64 * Cycle time -- 1.33 s (All instructions are one word.) * Halt mode -- The microcontroller operating clock is stopped in halt mode. There are four conditions that can clear halt mode: an interrupt request, a timer flip-flop overflow, a PA port input, or a HOLD pin input. * Operating supply voltage -- 4.5 to 5.5 V (Microcontroller block only: 3.5 to 5.5 V) * Package -- QIP100E * OTP version -- LC72P3700 * Development tools -- Emulator :RE32N -- Evaluation chip: LC72EV3700 -- Evaluation chip board: EB-72EV3700
Package Dimensions
unit: mm 3151-QFP100E
[LC723732/40/48/56/64]
SANYO: QFP100E
No. 5931-2/14
LC723732/40/48/56/64 Pin Assignment
No. 5931-3/14
LC723732/40/48/56/64 Block Diagram
No. 5931-4/14
LC723732/40/48/56/64
Specifications
Electrical Characteristics Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Symbol VDD max VIN1 VIN2 VOUT1 VOUT2 IOUT1 Output current Allowable power dissipation Operating temperature Storage temperature IOUT2 Pd max Topg Tstg PC-PORT All input pins other than VIN1 PC, PJ-PORT All output pins other than VOUT1 PC, PJ-PORT PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP, PQ, PR, PS, PT, PT-PORT, EO1, EO2, EO3, SUBPD Ta = -40 to +85C Conditions Ratings -0.3 to +6.5 -0.3 to +15 -0.3 to VDD + 0.3 -0.3 to +15 -0.3 to VDD + 0.3 0 to +5 0 to +3 400 -40 to +85 -45 to +125 Unit V V V V V mA mA mW C C
Output voltage
Allowable Operating Ranges at Ta = -40 to +85C, VDD = 3.5 to 5.5 V
Parameter Symbol VDD1 Supply voltage VDD2 VDD3 VIH1 Input high-level voltage Conditions CPU and PLL operating CPU operating Memory retention PB, PC, PH, PI, PL, PM, PN, PO, PP, PQ, PR, PS, PT-PORT, HCTR, LCTR, E03, SUBPD (with the I/O ports set to input mode.) PD, PE, PF, PG, PK-PORT, LCTR, (in period measurement mode), HOLD, RESET SNS PA-PORT PB, PC, PH, PI, PL, PM, PN, PO, PP, PQ, PR, PS, PT-PORT, HCTR, LCTR, E03, SUBPD (with the I/O ports set to input mode.) PA, PD, PE, PF, PG, PK-PORT, LCTR (in period measurement mode), RESET SNS HOLD XIN FMIN VIN2, VDD1 FMIN VIN3, VDD1 AMIN(H) VIN3, VDD1 AMIN(L) VIN3, VDD1 HCTR VIN3, VDD1 LCTR VIN3, VDD1 LCTR(period measurement) VIH2, VIL2, VDD1 XIN FMIN FMIN, AMIN, HCTR, LCTR ADI0 to ADI7 Ratings min 4.5 3.5 1.3 0.7 VDD typ 5.0 max 5.5 5.5 5.5 VDD Unit V V V V
VIH2 VIH3 VIH4 VIL1
0.8 VDD 2.5 0.6 VDD 0
VDD VDD VDD 0.3 VDD
V V V V
Input low-level voltage
VIL2 VIL3 VIL4 fIN1 fIN2 fIN3 fIN4
0 0 0 4.0 10 10 2.0 0.5 0.4 100 1 0.5 0.07 0.04 0 4.5
0.2 VDD 1.3 0.4 VDD 5.0 150 130 40 10 12 500 20 x 10
3
V V V MHz MHz MHz MHz MHz MHz kHz Hz Vrms Vrms Vrms V
Input frequency
fIN5 fIN6 fIN7 fIN8 VIN1
1.5 1.5 1.5 VDD
Input amplitude
VIN2 VIN3 VIN4
Input voltage range
No. 5931-5/14
LC723732/40/48/56/64 Electrical Characteristics in the allowable operating ranges
Parameter Symbol IIH1 IIH2 Conditions XIN: VI = VDD = 5.0 V FMIN, AMIN, HCTR, LCTR: VI = VDD = 5.0 V PA, PB, PC, PD, PE, PF, PG, PH, PI, PK, PL, PM, PN, PO, PP, PQ, PR, PS, PT-PORT, SNS, HOLD, RESET, HCTR, LCTR, E03, SUBPD: VI = VDD = 5.0 V (With the port PA pull-down resistors disabled, and PB, PC, PD, PE, PF, PG, PK, PL, PM, PN, PP, PO, PQ, PR, PS, and PT ports set to input mode.) Port PA (pull-down resistors enabled): VI = VDD = 5.0 V XIN: VI = VSS FMIN, AMIN, HCTR, LCTR: VI = VSS PA, PB, PC, PD, PE, PF, PG, PH, PI, PK, PL, PM, PN, PO, PP, PQ, PR, PS, PT-PORT, SNS, HOLD, RESET, HCTR, LCTR, E03, SUBPD: VI = VSS (With the port PA pull-down resistors disabled, and PB, PC, PD, PE, PF, PG, PK, PL, PM, PN, PP, PO, PQ, PR, PS, and PT ports set to input mode.) Port PA (pull-down resistors enabled) PD, PE, PF, PG, PK-PORT, RESET, LCTR(in period measurement mode) PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP, PQ, PR, PS, PT-PORT: IO = -1 mA EO1, EO2, EO3, SUBPD: IO = -500 A XOUT: IO = -200 A PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP, PQ, PR, PS, PT-PORT: IO = 1 mA E01, E02, E03, SUBPD: IO = 500 A XOUT: IO = 200 A PC, PJ-PORT: IO = 5 mA PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP, PQ, PR, PS, PT-PORT E01, E02, E03, SUBPD PC, PJ-PORT ADI0 to ADI7 VDD1 PREJ VDET RPD1 RPD2 IDD1 IDD2 Current drain IDD3 IDD4 Port PA (pull-down resistors enabled): VDD = 5 V TEST1, TEST2 During normal operation (PLL operating) VDD1, fIN2 = 130 MHz Ta = 25C Halt mode (CPU operation stopped, crystal oscillator operating) (See figure 1.) VDD2, Ta = 25C* Backup mode (crystal oscillator stopped) (See figure 2.) VDD = 5.5 V, Ta = 25C Backup mode (crystal oscillator stopped) (See figure 2.) VDD = 2.5 V, Ta = 25C SNS 2.6 75 3.0 100 10 20 30 -3.0 -100 -5.0 -1.5 0.1 VDD VDD - 1.0 VDD - 1.0 VDD - 1.0 1.0 1.0 1.5 2.0 3.0 100 5.0 1.5 50 3.4 200 0.2 VDD 2.0 4.0 50 5.0 10 15 30 Ratings min 2.0 4.0 typ 5.0 10 max 15 30 Unit A A
Input high-level current
IIH3
3.0
A
IIH4 IIL1 IIL2
A A A
Input low-level current IIL3
3.0
A
Input floating voltage Hysteresis
VIF VH VOH1
0.05 VDD
V V V V V V V V V A nA A LSB sec V k k mA
Output high-level voltage
VOH2 VOH3 VOL1
Output low-level voltage
VOL2 VOL3 VOL4 IOFF1
Output off leakage current
IOFF2 IOFF3
A/D conversion error Rejected pulse width Power down detection voltage Pull-down resistance
0.45
mA
5 1
A A
Note *: Twenty instruction steps are executed every millisecond. The PLL, universal counter, and other functions are stopped.
No. 5931-6/14
LC723732/40/48/56/64 Test Circuits
Note: Ports PB through PG, and PJ through PT are all left open. However, ports PB through PG, PK through PT, EO3, and SUBPD are left open in output mode.
Note: Ports PA through PT are all left open.
Figure 1 IDD2 in Halt Mode Pin Descriptions
Pin No. Symbol I/O Function
Figure 2 IDD3 and IDD4 in Backup Mode
Equivalent circuit
32 31 30 29
PA0 PA1 PA2 PA3 I
Dedicated input ports. These ports are designed with a low threshold voltage. The pull-down resistors for all four pins are set up together with an IOS1 instruction. The pull-down resistors cannot be set individually. Input is disabled in backup mode.
28 27 26 25
PB0 PB1 PB2 PB3 I/O
General-purpose I/O ports The mode (input or output) is set using the IOS2 instruction. Input is disabled and the pins go to the high-impedance state in backup mode. These ports are set up as general-purpose input ports after a power on reset.
24 23 22 21
PC0 PC1 PC2 PC3 I/O
General-purpose I/O ports (high-voltage input and output) The mode (input or output) is set using the IOS2 instruction. External pull-up resistors are required since the output circuits are open drain circuits. Input is disabled and the pins go to the high-impedance state in backup mode. These ports are set up as general-purpose input ports after a power on reset.
20 19 18 17
PD0/INT4 PD1/INT5 PD2 PD3 I/O
General-purpose I/O and external interrupt shared function ports The input formats are Schmitt inputs. The external interrupt function is enabled when the external interrupt enable flag is set. * When used as general-purpose I/O ports: The mode (input or output) is set in 1-bit units using the IOS2 instruction. * When used as external interrupt pins: The external interrupt functions are enabled by setting the corresponding external interrupt enable flag (INT4EN or INT5EN). Here, the pins must be set to input mode in advance. Input is disabled and the pins go to the high-impedance state in backup mode. These ports are set up as general-purpose input ports after a power on reset.
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Pin No. Symbol I/O Function General-purpose I/O ports with shared functions as serial I/O ports The input formats are Schmitt inputs. The PE1/SCK2 and PE2/SO2 pins can be switched to function as open drain outputs. The IOS1 instruction is used to switch between the general-purpose I/O port and serial I/O port functions. * When used as general-purpose I/O ports: The pins are set to the general-purpose I/O port function using the IOS1 instruction. The mode (input or output) is set in 1-bit units using the IOS1 instruction. * When used as serial I/O ports: The pins are set to the serial I/O port function using the IOS1 instruction. [Pin states when set to the serial I/O port function] PE0, PF0, PG0 ... General-purpose I/O PE1, PF1, PG1 ... SCK input or output PE2, PF2, PG2 ... SO output PE3, PF3, PG3 ... SI input The PE1/SCK2 and PE2/SO2 pins can be switched to function as open drain outputs with the IOS2 instruction. When using this circuit type, the external pull-up resistors must be connected to the same power supply as that used by the IC. Input is disabled and the pins go to the high-impedance state in backup mode. These ports are set up as general-purpose input ports after a power on reset. Equivalent circuit
16 15 14 13 12 11 10 9 8 7 6 5
PE0 PE1/SCK2 PE2/S02 PE3/SI2 PF0 PF1/SCK1 PF2/S01 PF3/SI1 PG0 PG1/SCK0 PG2/S00 PG3/SI0 I/O
1 100
XIN XOUT
I O
Connections for a 4.5-MHz crystal oscillator element
98 97
E01 E02
O
Main charge pump outputs These pins output a high level when the frequency of the local oscillator divided by n is higher than that of the reference frequency, and they output a low level when that frequency is lower. They go to the high-impedance state when the frequencies match. These pins go to the high-impedance state in backup mode, after a power on reset, and in the PLL stopped state. Power supply connections The VDDPORT and VSSPORT pins mainly supply power for the peripheral I/O blocks and the regulator. The VDDPLL and VSSPLL pins mainly for the PLL circuits. The VSSCPU pin is mainly used by the CPU block. The VSSADC pin is mainly used by the A/D converter block. Since all the VDD and VSS pins are independent, all must be connected to the same power supply. Internal low voltage output Connect a bypass capacitor to this pin. FM VCO (local oscillator) input This pin is selected with CW1 in the PLL instruction. The signal input to this pin must be capacitor coupled. Input is disabled in backup mode, after a power on reset, and in the PLL stopped state. AM VCO (local oscillator) input This pin is selected and the band set with CW1 (b1, b0) in the PLL instruction. b1 1 b0 0 1 Band 2 to 40 MHz (SW) 0.5 to 10 MHz (MW, LW)
39 93 4 40 81 96 3
VDDPORT VDDPLL VSSCPU VSSPORT VSSADC VSSPLL VREG O --
95
FMIN
I
94
AMIN
I
1
The signal input to this pin must be capacitor coupled. Input is disabled in backup mode, after a power on reset, and in the PLL stopped state.
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No. 5931-8/14
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Pin No. Symbol I/O Function Sub-charge pump output and general-purpose input shared function port The IOS2 instruction is used for switching between the sub-charge pump output and general-purpose input functions. * When used as the sub-charge pump output: The sub-charge pump output function is set up with the IOS2 instruction. A high-speed locking circuit can be formed by using this pin in conjunction with the main charge pump. The sub-charge pump is controlled using the DZC instruction. b3 92 SUBPD I/O 0 0 1 1 b2 0 1 0 1 High impedance Only operates when the PLL is unlocked (450 kHz) Only operates when the PLL is unlocked (900 kHz) Normal operation Operation Equivalent circuit
* When used as a general-purpose input: The general-purpose input function is set up with the IOS2 instruction. Data is read from the port using the INR instruction. This pin goes to the high-impedance state in backup mode, after a power on reset, and in the PLL stopped state.
91
E03
I/O
Second PLL charge pump output and general-purpose input shared function port The IOS2 instruction is used for switching between the second PLL charge pump output and general-purpose input functions. * When used as a charge pump output: The charge pump output function is set up with the IOS2 instruction. This pin outputs a low level when the frequency of the local oscillator divided by n is higher than that of the reference frequency, and it outputs a high level when that frequency is lower. It goes to the high-impedance state when the frequencies match. (Note that the logic of this pin is inverted from that of the EO1 and EO2 pins.) * When used as a general-purpose input: The general-purpose input function is set up with the IOS2 instruction. Data is read from the port using the INR instruction. This pin goes to the high-impedance state in backup mode, after a power on reset, and in the PLL stopped state. Universal counter and general-purpose input shared function input port The IOS1 instruction is used for switching between the universal counter and general-purpose input functions. * When used for frequency measurement: The universal counter function is set up with the IOS1 instruction. The counter is controlled using the UCS and UCC instructions. Since this pin functions as an AC amplifier in this mode, the input signal must be input with capacitor coupling. * When used as a general-purpose input pin: The general-purpose input function is set up with the IOS1 instruction. Data is read from the port using the INR (b0) instruction. Input is disabled in backup mode. (The input pin will be pulled down.) The universal counter function is selected after a power on reset. Universal counter (frequency or period measurement) and general-purpose input shared function input port The IOS1 instruction is used for switching between the universal counter and general-purpose input functions. * When used for frequency measurement: The universal counter function is set up with the IOS1 instruction. Set up LCTR frequency measurement mode with the UCS instruction, and control operation with the UCC instruction. Since this pin functions as an AC amplifier in this mode, the input signal must be input with capacitor coupling. * When used for period measurement: The universal counter function is set up with the IOS1 instruction. Set up LCTR frequency measurement mode with the UCS instruction, and control operation with the UCC instruction. Since the bias feedback resistor is disconnected in this mode, the input signal must be input with DC coupling. * When used as a general-purpose input pin: The general-purpose input port function is set up with the IOS1 instruction. Data is read from the port using the INR (b1) instruction. Input is disabled in backup mode. (The input pin will be pulled down.) The universal counter function (HCTR frequency measurement mode) is selected after a power on reset.
90
HCTR
I
89
LCTR
I
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Pin No. Symbol I/O Function Voltage sense and general-purpose input shared function port This input circuit is designed with a low input threshold voltage. * When used as a voltage sense input: This pin is used to test for power failures on the return from backup mode. Application can test this condition using the internal SNS flip-flop. The SNS flip-flop can be tested with the TST instruction. (This usage requires external components (capacitors and resistors). See the sample application circuit in the user's manual.) * When used as a general-purpose input port: When used as a general-purpose input port the pin state can be tested with the TST instruction. Unlike the other input ports, input to this pin is not disabled in backup mode and after a power on reset. As a result, through currents must be taken into account when designing applications that use this pin as a general-purpose input. Power supply monitor (with interrupt function) This pin is designed with a high input threshold voltage. This pin is normally connected to the ACC line and used for power off detection. When a power off state is detected, the HOLDON flag and the hold interrupt request flag will be set. To enter backup mode, execute a CKSTP instruction when the HOLD pin is low. Set this pin high to clear backup mode. System reset pin When the CPU is operating or in halt mode, the system is reset when this pin is held low for at least one machine cycle. Execution starts with the PC pointing to location 0. At this time the SNS flip-flop is set. A low level must be applied for at least 50 ms when power is first applied. General-purpose input and A/D converter input shared function ports The IOS1 instruction is used to switch between the general-purpose input and the A/D converter input functions. * When used as a general-purpose input ports: The general-purpose input port function is set up with the IOS1 instruction. (In bit units) * When used as A/D converter input pins: The A/D converter input port function is set up with the IOS1 instruction. (In bit units) The pin whose voltage is to be converted is specified with the IOS1 instruction, and the conversion is started with the UCC instruction. Note: Since input is disabled for ports specified for the ADI function, executing an input instruction for such a port will always return a low level. Input is disabled in backup mode. These ports are set up as general-purpose input ports after a power on reset. Equivalent circuit
88
SNS
I
87
HOLD
I
86
RESET
I
85 84 83 82 81 80 79 78
PH0/ADI0 PH1/ADI1 PH2/ADI2 PH3/ADI3 PI0/ADI4 PI1/ADI5 PI2/ADI6 PI3/ADI7 I
76 75 74 73
PJ0 PJ1 PJ2 PJ3 O
General-purpose output ports Since these are open-drain output circuits, external pull-up resistors are required. The internal transistors are turned off (resulting in a high-level output) in backup mode and after a power on reset.
72 71 70 69
PK0/INT0 PK1/INT1 PK2/INT2 PK3/INT3 I/O
General-purpose I/O and external interrupt shared function ports The input formats are Schmitt inputs. The external interrupt function is enabled when the external interrupt enable flag is set. * When used as general-purpose I/O ports: The mode (input or output) is set in 1-bit units using the IOS1 instruction. * When used as external interrupt pins: The external interrupt functions are enabled by setting the corresponding external interrupt enable flag (INT0EN through INT3EN). Here, the pins must be set to input mode in advance. Input is disabled and the pins go to the high-impedance state in backup mode. These ports are set up as general-purpose input ports after a power on reset.
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No. 5931-10/14
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Pin No. Symbol PL0 to 3 PN0 to 3 I/O Function General-purpose I/O ports The mode is switched between input and output with the IOS instruction. Input is disabled and the pins go to the high-impedance state in backup mode. These ports are set up as general-purpose input ports after a power on reset. General-purpose I/O port and beep tone output shared function ports The IOS2 instruction is used to switch between the general-purpose I/O port and the beep tone output functions. * When used as a general-purpose input ports: The general-purpose I/O port function is set up with the IOS2 instruction. (Pins PN1 through PN3 are general-purpose I/O pins.) * When used as the beep tone output pin: The beep tone output function is set up with the IOS2 instruction. The frequency is set with the BEEP instruction. When this pin is used as the beep tone output pin, executing an output instruction for this pin only sets the internal latch and has no influence on the output. Input is disabled and the pins go to the high-impedance state in backup mode. These ports are set up as general-purpose input ports after a power on reset. General-purpose I/O ports The mode is switched between input and output with the IOS instruction. Input is disabled and the pins go to the high-impedance state in backup mode. These ports are set up as general-purpose input ports after a power on reset. Equivalent circuit
68 to 61
I/O
60 59 58 57
PN0/BEEP PN1 PN2 PN3 I/O
56 to 49
P00 to 3 PP0 to 3
I/O
PQ0 to 3 48 to 41 38 to 33 PR0 to 3 PS0 to 3 PT0 to 1 I/O
General-purpose I/O ports The mode is switched between input and output with the IOS instruction, and data is input with the INR instruction and output with the OUTR instruction. The SPB, RPB, TPT, and TPF instruction cannot be used with these ports. Input is disabled and the pins go to the high-impedance state in backup mode. These ports are set up as general-purpose input ports after a power on reset.
99 2
TEST1 TEST2
IC test pins These pins must be tied to ground.
No. 5931-11/14
LC723732/40/48/56/64 LC723700 Instruction Set Abbreviations ADDR: b: c: DH: DL: I: M: N: MADR: ROMADR: P1n, P2n: PW1n, PW2n: PEn: SR: ADR: DTR: r: SWR: SRR: ( ), [ ]: M(DH, DL):
Instruction group Mnemonic AD Addition instructions ADS AC ACS AI AIS AIC AICS SU Subtraction instructions SUS SB SBS SI SIS SIB SIBS Comparison instructions SEQ SEQI SNEI SGE SLE SGEI SLEI
Program memory address Borrow Carry Data memory address High (Row address) [2 bits] Data memory address Low(Column address) [4 bits] Immediate data [4 bits] Data memory address Bit position [4 bits] M specified by address register Program memory data specified by address register Port number [4 bits] Port control word number [4 bits] Peripheral register number [4 bits] ADR/DTR Address register Data register General register (One of the address from 00H to 0FH of BANK0) Status write register Status read register Contents of register or memory Data memory specified by DH, DL
Operand 1st r r r r M M M M r r r r M M M M r M M r r M M 2nd M M M M I I I I M M M M I I I I M I I M M I I Add M to r ADD M to r, then skip if carry Add M to r with carry Add M to r with carry, then skip if carry Add I to M Add I to M, then skip if carry Add I to M with carry Add I to M with carry, then skip if carry Subtract M from r Subtract M from r, then skip if borrow Subtract M from r with borrow Subtract M from r with borrow, then skip if borrow Subtract I from M Subtract I from M, then skip if borrow Subtract I from M with borrow Subtract I from M with borrow, then skip if borrw Skip if r equal to M Skip if M equal to I Skip if M not equal to I Skip if r is greater than or equal to M Skip if r is less than M Skip if M is greater than or equal to I Skip if M is less than I Function Operations function r (r) + (M) r (r) + (M), skip carry r (r) + (M) + C r (r) + (M) + C skip if carry M (M) + I M (M) + I, skip if carry M (M) + I + C M (M) + I + C, skip if carry r (r) - (M) r (r) - (M), skip if borrow r (r) - (M) - b Instruction format fedcba9876543210 0 1 0 0 0 0 DH 0 1 0 0 0 1 DH 0 1 0 0 1 0 DH 0 1 0 0 1 1 DH 0 1 0 1 0 0 DH 0 1 0 1 0 1 DH 0 1 0 1 1 0 DH 0 1 0 1 1 1 DH 0 1 1 0 0 0 DH 0 1 1 0 0 1 DH 0 1 1 0 1 0 DH DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL r r r r I I I I r r r r I I I I r I I r r I I
r (r) - (M) -b, skip if borrow 0 1 1 0 1 1 DH M (M) - I M (M) - I, skip if borrow M (M) - I - b 0 1 1 1 0 0 DH 0 1 1 1 0 1 DH 0 1 1 1 1 0 DH
M (M) - I -b, skip if borrow 0 1 1 1 1 1 DH (r) - (M), skip if zero (M) - I, skip if zero (M) - I, skip if not zero (r) - (M), skip if not borrow (r) - M, skip if borrow (M) - I, skip if not borrow (M) - I, skip if borrow 0 0 0 1 0 0 DH 0 0 0 1 0 1 DH 0 0 0 0 0 1 DH 0 0 0 1 1 0 DH 0 0 0 0 1 0 DH 0 0 0 1 1 1 DH 0 0 0 0 1 1 DH
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Instruction group Mnemonic AND Logical operation instructions ANDI OR ORI EXL EXLI SHMR LD ST Transfer instructions LDA STA MVRD MVRS MVSR MVI Bit test instructions TMT TMF JMP JMPA JMPR Jump and subroutine instructions CAL CALA RT RTS RTB RTBS ADDR ADDR r M M1 M M M ADDR r M r r M r M2 I N N Operand 1st r M r M r M M M r 2nd M I M I M I AND M with r AND I with M OR M with r OR I with M Exclusive OR M with r Exclusive OR M with M Shift M right with carry Load M to r Strore r to M Load M specified by ADR to r Store r to M specified by ADR Move M to destination M referring to r in the same row Move source M referring to r to M in the same row Move M to M in the same row Move I to M Test M bits, then skip if all bits specified are true Test M bits, then skip if all bits specified are false Jump to the address Jump to the address specified by ADR Jump to the relative address Call subroutine Call subroutine specified by ADR Return from subroutine Return from subroutine and skip Return from subroutine with BANK data Return from subroutine with BANK data and skip r (M) M (r) r (MADR) MADR (r) [DH, rn] (M) M (DH, rn) [DH, DL1] [DH, DL2] MI if M(N) = all 1, then skip if M(N) = all 0, then skip PC ADDR PC (ADR) PC (PC) + 1 + ADDR PC ADDR Stack (PC) + 1 PC (ADR) Stack (PC) + 1 PC Stack PC Stack + 1 PC Stack, BANK Stack PC Stack + 1, BANK Stack PC Stack, BANK Stack, CARRY Stack PAGE Stack (Status W-reg)N 1 (Status W-reg)N 0 Function Operations function r (r) AND (M) M (M) AND I r (r) OR (M) M (M) OR I r (r) XOR (M) M (M) XOR I carry (M) Instruction format fedcba9876543210 0 0 1 0 0 0 DH 0 0 1 0 0 1 DH 0 0 1 0 1 0 DH 0 0 1 0 1 1 DH 0 0 1 1 0 0 DH 0 0 1 1 0 1 DH DL DL DL DL DL DL r I r I r I DL r r r r r r DL2 I N N
1 1 1 1 1 1 1 1 1 0 DH 1 1 0 1 0 0 DH 1 1 0 1 0 1 DH DL DL
111110011100 111110011101 1 1 0 1 1 0 DH 1 1 0 1 1 1 DH 1 1 1 0 0 0 DH 1 1 1 0 0 1 DH 1 1 1 1 0 0 DH 1 1 1 1 0 1 DH 10 DL DL DL DL DL DL
ADDR(14 bits)
000000001110 11111010 1100 ADDR (8 bits)
ADDR(12 bits)
000000001111 000000001000 000000001010 111111111100 111111111101
RTI
Return from interrupt
000000001001
Status register instructions
SS RS TST TSF PLL PUT GET SIO UCS UCC BEEP DZC TMS IOS1 IOS2
SWR SWR SRR SRR M PEn PEn I1 I I I I I PW1n PW2n
N N N N
Set status register Reset status register Test status register true Test status register false Load M to PLL register Put data of DTR to perifheral register Get peripheral data to DTR
1 1 1 1 1 1 1 1 0 0 SWR 1 1 1 1 1 1 1 1 0 1 SWR SRR SRR
N N N N DL PEn PEn I2 I I I I I N N
if (Status R-reg)N = all1, then skip 1 1 1 1 1 0 0 0 0 if (Status R-reg)N = all0, then skip 1 1 1 1 1 0 0 0 1 PLL reg PLL data PEn (DTR) DTR (PEn) SIO reg I1, I2 UCCW1 I UCCW2 I BEEP reg I DZC reg I Timer reg I IOS1 reg PW1n N IOS2 reg PW2n N
Internal register transfer instructions
1 1 1 1 1 0 0 1 0 1 DH 111110011010 111110011011 00000001 I1
Hardware control instructions
I2
Serial I/O control Set I to UCCW1 Set I to UCCW2 Beep control Dead zone control Set timer register
000000000001 000000000010 000000000110 000000001011 000000001100 11111110 11111011 PW1n PW2n
N N
Set port control word1 Set port control word2
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LC723732/40/48/56/64
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Instruction group Mnemonic IN OUT I/O instructions INR OUTR SPB RPB TPT TPF Table reference Bank switching instructions instructions Operand 1st M M M M P1n P1n P1n P1n 2nd P1n P1n P2n P2n N N N N Function Input port1 data to M Output contents of M to port 1 Input port 2 data to M Output contents of M to port 2 Set port 1 bits Reset port 1 bits Test port 1 bits, then skip if all bits specified are true Test port 1 bits, then skip if all bits specified are false Operations function M (P1n) P1n M M (P2n) P2n (M) (P1n)N 1 (P1n)N 0 if (P1n)N = all 1, then skip if (P1n)N = all 0, then skip Instruction format fedcba9876543210 1 1 1 0 1 0 DH 1 1 1 0 1 1 DH 0 0 1 1 1 0 DH 0 0 1 1 1 1 DH 00000010 00000011 11111100 11111101 DL DL DL DL P1n P1n P1n P1n P1n P1n P2n P2n N N N N
BANK
I
Select Bank
BANK I
1111100100
I
MVTL
Move program memory data specified by ADR to DTR
DTR (ROMADR)
000000000011
Stack manipulation instructions
PUSH
SR
Move ADR/DTR to stack
Stack (ADR/DTR) ADR/DTR Stack PAGE flag I HALT reg I, then CPU clock stop Stop xtal OSC if HOLD = 0 No operation
111110011000
SR
POP PAGE
SR I I
Move stack to ADR/DTR Set page flag Halt mode control Clock stop No operation
111110011001 000000000111 000000000100 000000000101 000000000000
SR I I
Other instructions
HALT CKSTP NOP
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1998. Specifications and information herein are subject to change without notice. PS No. 5931-14/14

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